Freescale-semiconductor StarCore SC140 Manual de usuario descargar pdf (Pagina 195)

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Instruction Timing

SC140 DSP Core Reference Manual 5-15

Table 5-5 summarizes the timing of the various categories of SC140 instructions.

Table 5-5. Instruction Categories Timing Summary

5.3.1 Sequential Instruction Timing

This section describes the timing of non-COF instructions:

• All DALU instructions take one clock cycle to execute.

• All AGU arithmetic instructions take one cycle to execute.

• All memory MOVE instructions (zero-wait-states without contention) take one clock cycle to

execute, unless the addressing mode needs to perform a pre-calculation, in which case, the move

executes in two cycles. For example, the move instructions below take two cycles:

— MOVE.L d0,(Rn + N0)

— MOVE.L d0,(Rn + $5)

— MOVE.L d0,(Rn + Rm)

— MOVE.L d0,(SP + $100)

• All bit mask (BMU) instructions execute in two cycles on registers and memory (zero-wait-states

without contention) with simple addressing modes. However, if a pre-calculation is required, such

as an SP offset, a third cycle is added.

Basic Instruction Category Example/Condition Number of Clock Cycles

DALU MAC D0, D1, D2 1

Data move with simple addressing MOVE.W (R0)+N2, D3 1

Data move with address pre-calculation MOVE.W (R5+N0), D4 2

BMU with simple addressing BMSET.W #$1010, (R0) 2

BMU with address pre-calculation BMSET.W #$1010,(SP+$10) 3

Direct change-of-flow JMP dest 3

PC-relative change-of-flow BRA dest 4

Conditional change-of-flow If condition is true 4

If condition is false 1

Delayed change-of-flow Direct 3 (some cycles used by the

execution set in the delay slot)

PC-relative 4 (some cycles used by the

execution set in the delay slot)

1 2 ... 190 191 192 193 194 195 196 197 198 199 200 ... 759 760

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