Freescale-semiconductor StarCore SC140 Manual de usuario descargar pdf (Pagina 175)

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Trace Unit Registers

SC140 DSP Core Reference Manual 4-65

4.10.5 Event Selector Mask Disable Trace Register

(ESEL_DTB)

This 16-bit register has one bit for every source of the ES. Setting the appropriate bit configures the related

source to cause a disable trace.

Figure 4-27 displays the bit configuration of ESEL_DTB.

Figure 4-27. Event Selector Mask Disable Trace (ESEL_DTB)

If multiple sources are configured to disable trace, they are ANDed or ORed according to the value of the

SELDTB bit in the ESEL_CTRL. See Section 4.10.1, “Event Selector Control Register (ESEL_CTRL),”

for further details. If all the bits are set to zero, the ES does not issue a disable trace.

The same event cannot be configured to both enable and disable tracing.

4.11 Trace Unit Registers

The trace unit includes the following registers:

• Trace Buffer Control Register (TB_CTRL)

• Trace Buffer Read Pointer Register (TB_RD)

• Trace Buffer Write Pointer Register (TB_WR)

• Trace Buffer Virtual Register (TB_BUFF)

4.11.1 Trace Buffer Control Register (TB_CTRL)

The TB_CTRL register controls the operation of the trace unit. The following tracing modes are possible,

all which trace the PC of execution sets that answer some conditions:

• TEXEXT - trace the PC of every execution set

• TMARK - trace the PC of execution sets that includes the MARK instruction

• TCHOF - trace the source and destination PC of execution set that includes

a taken COF instruction (listed in Table A-13 in Appendix A, not including

TRAP, but including the BREAK, CONT/D instructions)

• TLOOP - trace the exection of HW loops.

For long loops, the PC of the last address (LA) and start address (SA) are traced.

For short loops, only the PC of LA is traced.

• TINT - trace the interrupt point and destination PC of interrupts and exceptions

(including the TRAP, and ILLEGAL instructions)

TEXEC and TMARK can only be activated on their own, without other tracing options enabled.

BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0

DEBUGE

EE4 EE3 EE2 EE1 EE0

COUN

EDCD

EDCA

TYPE rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1 2 ... 170 171 172 173 174 175 176 177 178 179 180 ... 759 760

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