Freescale-semiconductor 56F8122 Manual de usuario

56F830016-bit Hybrid Controllersfreescale.com56F8322/56F8122Data SheetPreliminary Technical DataMC56F8322Rev. 10.010/2004

56F8322 Techncial Data, Rev. 10.010 Freescale SemiconductorPreliminaryFigure 1-1 System Bus InterfacesNote: Flash memories are encapsulated within th

56F8322 Techncial Data, Rev. 10.0100 Freescale SemiconductorPreliminaryNote: The 56F8122 device is specified to meet Industrial requirements only; P

General Characteristics56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 101Preliminary1. Theta-JA determined on 2s2p test boards is frequently

56F8322 Techncial Data, Rev. 10.0102 Freescale SemiconductorPreliminaryNote: The 56F8122 device is guaranteed to 40MHz and specified to meet Industr

DC Electrical Characteristics56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 103Preliminary10.2 DC Electrical CharacteristicsNote: The 56F

56F8322 Techncial Data, Rev. 10.0104 Freescale SemiconductorPreliminaryTable 10-6 Power-On Reset Low Voltage ParametersCharacteristic Symbol Min Typ

DC Electrical Characteristics56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 105Preliminary10.2.1 Voltage Regulator SpecificationsThe 56F832

56F8322 Techncial Data, Rev. 10.0106 Freescale SemiconductorPreliminaryTable 10-9. Regulator ParametersCharacteristic Symbol Min Typical Max UnitUn

AC Electrical Characteristics56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 107Preliminary10.2.2 Temperature SenseNote: Temperature Sensor i

56F8322 Techncial Data, Rev. 10.0108 Freescale SemiconductorPreliminaryFigure 10-1 Input Signal Measurement ReferencesFigure 10-2 shows the definitio

External Clock Operation Timing56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 109Preliminary10.5 External Clock Operation TimingFigure 10-

Architecture Block Diagram56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 11PreliminaryFigure 1-2 Peripheral SubsystemIPBusTimer ASPI 0ADCA26

56F8322 Techncial Data, Rev. 10.0110 Freescale SemiconductorPreliminary10.6 Phase Locked Loop Timing10.7 Oscillator Parameters Table 10-14 PLL Ti

Oscillator Parameters56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 111PreliminaryNote: An LSB change in the tuning code results in an 82ps

56F8322 Techncial Data, Rev. 10.0112 Freescale SemiconductorPreliminaryFigure 10-4 Frequency versus TemperatureFrequency in MHzTemperature- 50- 30- 1

Reset, Stop, Wait, Mode Select, and Interrupt Timing56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 113Preliminary10.8 Reset, Stop, Wait, M

56F8322 Techncial Data, Rev. 10.0114 Freescale SemiconductorPreliminaryFigure 10-7 External Level-Sensitive Interrupt TimingFigure 10-8 Recovery from

Serial Peripheral Interface (SPI) Timing56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 115Preliminary10.9 Serial Peripheral Interface (SPI

56F8322 Techncial Data, Rev. 10.0116 Freescale SemiconductorPreliminary1Figure 10-9 SPI Master Timing (CPHA = 0)Figure 10-10 SPI Master Timing (CPHA

Serial Peripheral Interface (SPI) Timing56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 117PreliminaryFigure 10-11 SPI Slave Timing (CPHA = 0

56F8322 Techncial Data, Rev. 10.0118 Freescale SemiconductorPreliminary10.10 Quad Timer TimingFigure 10-13 Timer Timing10.11 Quadrature Decoder T

Serial Communication Interface (SCI) Timing56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 119PreliminaryFigure 10-14 Quadrature Decoder Timi

56F8322 Techncial Data, Rev. 10.012 Freescale SemiconductorPreliminaryTable 1-2 Bus Signal NamesName FunctionProgram Memory Interfacepdb_m[15:0] Prog

56F8322 Techncial Data, Rev. 10.0120 Freescale SemiconductorPreliminary10.13 Controller Area Network (CAN) TimingNote: CAN is NOT available in the

JTAG Timing56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 121PreliminaryFigure 10-18 Test Clock Input Timing DiagramFigure 10-19 Test Access

56F8322 Techncial Data, Rev. 10.0122 Freescale SemiconductorPreliminary10.15 Analog-to-Digital Converter (ADC) ParametersTable 10-24 ADC Parameters

Analog-to-Digital Converter (ADC) Parameters56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 123PreliminarySignal-to-noise plus distortion rat

56F8322 Techncial Data, Rev. 10.0124 Freescale SemiconductorPreliminaryFigure 10-20 ADC Absolute Error Over Processing and Temperature Extremes Befor

Equivalent Circuit for ADC Inputs56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 125Preliminary10.16 Equivalent Circuit for ADC InputsFigur

56F8322 Techncial Data, Rev. 10.0126 Freescale SemiconductorPreliminaryB, the internal [state-dependent component], reflects the supply curre

56F8322 Package and Pin-Out Information56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 127PreliminaryPart 11 Packaging11.1 56F8322 Package

56F8322 Techncial Data, Rev. 10.0128 Freescale SemiconductorPreliminaryTable 11-1 56F8322 48-Pin LQFP Package Identification by Pin NumberPin No. Sig

56F8122 Package and Pin-Out Information56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 129Preliminary11.2 56F8122 Package and Pin-Out Infor

Product Documentation56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 13Preliminary1.5 Product DocumentationThe documents listed in Table 1-

56F8322 Techncial Data, Rev. 10.0130 Freescale SemiconductorPreliminaryTable 11-2 56F8122 48-Pin LQFP Package Identification by Pin NumberPin No. Sig

56F8122 Package and Pin-Out Information56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 131PreliminaryFigure 11-3 48-Pin LQFP Mechanical Infor

56F8322 Techncial Data, Rev. 10.0132 Freescale SemiconductorPreliminaryPart 12 Design Considerations12.1 Thermal Design ConsiderationsAn estimatio

Electrical Design Considerations56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 133PreliminaryThe thermal characterization parameter is measu

56F8322 Techncial Data, Rev. 10.0134 Freescale SemiconductorPreliminary• Because the device’s output signals have fast rise and fall times, PCB trace

Power Distribution and I/O Ring Implementation56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 135PreliminaryPart 13 Ordering InformationTabl

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56F8322 Techncial Data, Rev. 10.014 Freescale SemiconductorPreliminaryPart 2 Signal/Connection Descriptions2.1 IntroductionThe input and output si

Introduction56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 15PreliminaryFigure 2-1 56F8322 Signals Identified by Functional Group (48-Pin LQ

56F8322 Techncial Data, Rev. 10.016 Freescale SemiconductorPreliminaryFigure 2-2 56F8122 Signals Identified by Functional Group (48-Pin LQFP)VDD_IOVD

Signal Pins56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 17Preliminary2.2 Signal PinsAfter reset, each pin is configured for its primary

56F8322 Techncial Data, Rev. 10.018 Freescale SemiconductorPreliminaryEXTAL(GPIOC0)32 Input/SchmittInput/OutputInputInputExternal Crystal Oscillator

Signal Pins56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 19PreliminaryPHASEA0(TA0)(GPIOB7)(oscillator_clock)38 SchmittInputSchmittInput/Out

56F8322 Techncial Data, Rev. 10.02 Freescale SemiconductorPreliminary Document Revision HistoryVersion History Description of ChangeRev 1.0Pre-Relea

56F8322 Techncial Data, Rev. 10.020 Freescale SemiconductorPreliminaryINDEX0(TA2)(GPIOB5)(SYS_CLK)36 SchmittInputSchmittInput/OutputSchmittInput/Outp

Signal Pins56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 21PreliminaryMOSI0(GPIOB2)18 SchmittInput/OutputSchmittInput/OutputTri-statedInput

56F8322 Techncial Data, Rev. 10.022 Freescale SemiconductorPreliminaryPWMA1(GPIOA1)4SchmittOutputSchmittInput/OutputTri-statedInputPWMA1 — This is on

Signal Pins56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 23PreliminaryPWMA4(MOSI1)(GPIOA4)8OutputSchmittInput/OutputSchmittInput/OutputTri-

56F8322 Techncial Data, Rev. 10.024 Freescale SemiconductorPreliminaryVREFP28 Input/OutputInput/OutputVREFP, VREFMID & VREFN — Internal pins for

Signal Pins56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 25PreliminaryIRQA(VPP)11 SchmittInputInputN/AExternal Interrupt Request A — The IR

56F8322 Techncial Data, Rev. 10.026 Freescale SemiconductorPreliminaryPart 3 On-Chip Clock Synthesis (OCCS)3.1 IntroductionRefer to the OCCS chapt

External Clock Operation56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 27Preliminary3.2.2 Ceramic Resonator (Default)It is also possible to

56F8322 Techncial Data, Rev. 10.028 Freescale SemiconductorPreliminary3.3 Use of On-Chip Relaxation OscillatorAn internal relaxtion oscillator can

Registers56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 29PreliminaryFigure 3-4 Internal Clock Operation3.5 Registers When referring to th

56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 3Preliminary 56F8322/56F8122 Block DiagramProgram Controllerand Hardware Looping UnitData ALU

56F8322 Techncial Data, Rev. 10.030 Freescale SemiconductorPreliminaryPart 4 Memory Map4.1 IntroductionThe 56F8322 and 56F8122 devices are 16-bit

Interrupt Vector Table56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 31PreliminaryNote: Program RAM is NOT available on the 56F8122 device.4

56F8322 Techncial Data, Rev. 10.032 Freescale SemiconductorPreliminarycore 6 1-3 P:$0C OnCE Step Countercore 7 1-3 P:$0E OnCE Breakpoint Unit 0Reserv

Interrupt Vector Table56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 33PreliminaryReservedTMRC 56 0-2 P:$70 Timer C Channel 0TMRC 57 0-2 P:$

56F8322 Techncial Data, Rev. 10.034 Freescale SemiconductorPreliminary4.4 Data MapNote: Data Flash is NOT available on the 56F8122 device.4.5 Fla

Flash Memory Map56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 35PreliminaryFigure 4-1 Flash Array Memory MapsTable 4-5 shows the page and s

56F8322 Techncial Data, Rev. 10.036 Freescale SemiconductorPreliminary4.6 EOnCE Memory Map4.7 Peripheral Memory Mapped RegistersOn-chip periphera

Peripheral Memory Mapped Registers56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 37PreliminaryThe following tables list all of the periphera

56F8322 Techncial Data, Rev. 10.038 Freescale SemiconductorPreliminaryTMRA0_CMPLD2 $9 Comparator Load Register 2TMRA0_COMSCR $A Comparator Status and

Peripheral Memory Mapped Registers56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 39PreliminaryTable 4-9 Quad Timer C Registers Address Map(T

56F8322 Techncial Data, Rev. 10.04 Freescale SemiconductorPreliminaryPart 1: Overview . . . . . . . . . . . . . . . . . . . . . . 51.1. 56F8322/56

56F8322 Techncial Data, Rev. 10.040 Freescale SemiconductorPreliminaryTMRC3_CMP2 $31 Compare Register 2TMRC3_CAP $32 Capture RegisterTMRC3_LOAD $33 L

Peripheral Memory Mapped Registers56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 41PreliminaryTable 4-11 Quadrature Decoder 0 Registers Addr

56F8322 Techncial Data, Rev. 10.042 Freescale SemiconductorPreliminaryIRQP 0 $11 IRQ Pending Register 0IRQP 1 $12 IRQ Pending Register 1IRQP 2 $13 IR

Peripheral Memory Mapped Registers56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 43PreliminaryADCA_HLMT 1 $1A High Limit Register 1ADCA_HLMT

56F8322 Techncial Data, Rev. 10.044 Freescale SemiconductorPreliminaryTable 4-16 Serial Communication Interface 1 Registers Address Map(SCI1_BASE = $

Peripheral Memory Mapped Registers56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 45PreliminaryTable 4-20 Clock Generation Module Registers A

56F8322 Techncial Data, Rev. 10.046 Freescale SemiconductorPreliminaryTable 4-23 GPIOC Registers Address Map(GPIOC_BASE = $00F310)Register Acronym Ad

Peripheral Memory Mapped Registers56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 47PreliminaryTable 4-26 Flash Module Registers Address Map(

56F8322 Techncial Data, Rev. 10.048 Freescale SemiconductorPreliminaryFCRX14MASK_H $A Receive Buffer 14 Mask High RegisterFCRX14MASK_L $B Receive Buf

Peripheral Memory Mapped Registers56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 49PreliminaryFCMB3_CONTROL $58 Message Buffer 3 Control / S

56F8322/56F8122 Features56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 5PreliminaryPart 1 Overview1.1 56F8322/56F8122 Features1.1.1 Hybri

56F8322 Techncial Data, Rev. 10.050 Freescale SemiconductorPreliminaryFCMB7_DATA $7C Message Buffer 7 Data RegisterFCMB7_DATA $7D Message Buffer 7 Da

Peripheral Memory Mapped Registers56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 51PreliminaryFCMB12_ID_HIGH $A1 Message Buffer 12 ID High R

56F8322 Techncial Data, Rev. 10.052 Freescale SemiconductorPreliminary4.8 Factory-Programmed MemoryThe Boot Flash memory block is programmed

Functional Description56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 53Preliminary5.3.2 Interrupt NestingInterrupt exceptions may be nested

56F8322 Techncial Data, Rev. 10.054 Freescale SemiconductorPreliminary5.4 Block DiagramFigure 5-1 Interrupt Controller Block Diagram5.5 Operating

Register Descriptions56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 55Preliminary5.6 Register DescriptionsA register address is the sum of

56F8322 Techncial Data, Rev. 10.056 Freescale SemiconductorPreliminaryFigure 5-2 ITCN Register Map SummaryAdd. OffsetRegister Name15 14 13 12 11 10 9

Register Descriptions56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 57Preliminary5.6.1 Interrupt Priority Register 0 (IPR0)Figure 5-3 Interr

56F8322 Techncial Data, Rev. 10.058 Freescale SemiconductorPreliminary5.6.2.1 Reserved—Bits 15–6This bit field is reserved or not implemented. It i

Register Descriptions56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 59Preliminary5.6.3.1 Flash Memory Command, Data, Address Buffers Empty

56F8322 Techncial Data, Rev. 10.06 Freescale SemiconductorPreliminary1.1.3 MemoryNote: Features in italics are NOT available in the 56F8122 device.•

56F8322 Techncial Data, Rev. 10.060 Freescale SemiconductorPreliminary5.6.3.5 Low Voltage Detector Interrupt Priority Level (LVI IPL)—Bits 7–6This

Register Descriptions56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 61Preliminary5.6.4.3 FlexCAN Wake Up Interrupt Priority Level (FCWKUP

56F8322 Techncial Data, Rev. 10.062 Freescale SemiconductorPreliminary5.6.5.1 SPI0 Receiver Full Interrupt Priority Level (SPI0_RCV IPL)—Bits 15–14

Register Descriptions56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 63Preliminary5.6.5.6 GPIO_B Interrupt Priority Level (GPIOB IPL)—Bits

56F8322 Techncial Data, Rev. 10.064 Freescale SemiconductorPreliminary5.6.6.3 SCI1 Receiver Error Interrupt Priority Level (SCI1_RERR IPL)—Bits 9–8

Register Descriptions56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 65Preliminary5.6.7 Interrupt Priority Register 6 (IPR6)Figure 5-9 Interr

56F8322 Techncial Data, Rev. 10.066 Freescale SemiconductorPreliminary5.6.8 Interrupt Priority Register 7 (IPR7)Figure 5-10 Interrupt Priority Regist

Register Descriptions56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 67Preliminary5.6.8.5 Timer C, Channel 1 Interrupt Priority Level (TMRC

56F8322 Techncial Data, Rev. 10.068 Freescale SemiconductorPreliminary5.6.9.4 SCI0 Transmitter Idle Interrupt Priority Level (SCI0_TIDL IPL)—Bits 9

Register Descriptions56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 69Preliminary5.6.9.8 Timer A, Channel 1 Interrupt Priority Level (TMRA

Device Description56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 7Preliminary1.1.5 Energy Information• Fabricated in high-density CMOS with

56F8322 Techncial Data, Rev. 10.070 Freescale SemiconductorPreliminary5.6.10.5 ADC A Zero Crossing or Limit Error Interrupt Priority Level(ADCA_ZC

Register Descriptions56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 71Preliminary5.6.12 Fast Interrupt 0 Match Register (FIM0)Figure 5-14 Fa

56F8322 Techncial Data, Rev. 10.072 Freescale SemiconductorPreliminary5.6.14.2 Fast Interrupt 0 Vector Address High (FIVAH0)—Bits 4–0The upper five

Register Descriptions56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 73Preliminary5.6.17.1 Reserved—Bits 15–5This bit field is reserved or

56F8322 Techncial Data, Rev. 10.074 Freescale SemiconductorPreliminary5.6.20 IRQ Pending 2 Register (IRQP2)Figure 5-22 IRQ Pending 2 Register (IRQP2)

Register Descriptions56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 75Preliminary5.6.23 IRQ Pending 5 Register (IRQP5)Figure 5-25 IRQ Pendin

56F8322 Techncial Data, Rev. 10.076 Freescale SemiconductorPreliminary5.6.30.2 Interrupt Priority Level (IPIC)—Bits 14–13These read-only bits refle

Resets56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 77Preliminary5.7 Resets5.7.1 Reset Handshake TimingThe ITCN provides the 56800E core

56F8322 Techncial Data, Rev. 10.078 Freescale SemiconductorPreliminary6.2 FeaturesThe SIM has the following features:• Flash security feature preve

Operating Mode Register56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 79Preliminary6.4 Operating Mode RegisterFigure 6-1 OMR The reset sta

56F8322 Techncial Data, Rev. 10.08 Freescale SemiconductorPreliminaryis programmable to support a continuously variable PWM frequency. Edge-aligned

56F8322 Techncial Data, Rev. 10.080 Freescale SemiconductorPreliminaryFigure 6-2 SIM Register Map Summary6.5.1 SIM Control Register (SIM_CONTROL)Figu

Register Descriptions56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 81Preliminary6.5.1.2 OnCE Enable (ONCE EBL)—Bit 5• 0 = OnCE clock to 5

56F8322 Techncial Data, Rev. 10.082 Freescale SemiconductorPreliminary6.5.2.3 COP Reset (COPR)—Bit 4When 1, the COPR bit indicates the Compu

Register Descriptions56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 83Preliminary6.5.4 Most Significant Half of JTAG ID (SIM_MSH_ID)This rea

56F8322 Techncial Data, Rev. 10.084 Freescale SemiconductorPreliminary6.5.6.3 IRQ—Bit 10This bit controls the pull-up resistors on the IRQA pin.6.5

Register Descriptions56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 85Preliminary6.5.7.4 INDEX0 (INDEX)—Bit 7• 0 = Peripheral output funct

56F8322 Techncial Data, Rev. 10.086 Freescale SemiconductorPreliminaryNote: PWM is NOT available in the 56F8122 device.As shown in Figure 6-10, the G

Register Descriptions56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 87Preliminary6.5.8.4 GPIOB1 (B1)—Bit 5This bit selects the alternate f

56F8322 Techncial Data, Rev. 10.088 Freescale SemiconductorPreliminary6.5.9.1 Reserved—Bits 15–14This bit field is reserved or not implemented. It

Register Descriptions56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 89Preliminary6.5.9.10 Serial Communications Interface 1 Enable (SCI1)—

Architecture Block Diagram56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 9Preliminary1.4 Architecture Block Diagram Note: Features in ital

56F8322 Techncial Data, Rev. 10.090 Freescale SemiconductorPreliminaryFigure 6-13 I/O Short Address DeterminationWith this register set, an interrupt

Clock Generation Overview56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 91Preliminary6.5.10.2 Input/Output Short Address Low (ISAL[21:6])—

56F8322 Techncial Data, Rev. 10.092 Freescale SemiconductorPreliminary6.8 Stop and Wait Mode Disable FunctionFigure 6-16 Internal Stop Disable Circ

Operation with Security Enabled56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 93PreliminaryPart 7 Security FeaturesThe 56F8322/56F8122 offe

56F8322 Techncial Data, Rev. 10.094 Freescale SemiconductorPreliminaryProper implementation of Flash security requires that no access to the E

Flash Access Blocking Mechanisms56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 95PreliminaryEXAMPLE 1: If the system clock is the 8MHz cryst

56F8322 Techncial Data, Rev. 10.096 Freescale SemiconductorPreliminaryPart 8 General Purpose Input/Output (GPIO)8.1 IntroductionThis section is

Configuration56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 97PreliminaryTable 8-3 GPIO External Signals MapPins in shaded rows are not avai

56F8322 Techncial Data, Rev. 10.098 Freescale SemiconductorPreliminary8.3 Memory MapsThe width of the GPIO port defines how many bits are implement

General Characteristics56F8322 Technical Data, Rev. 10.0Freescale Semiconductor 99PreliminaryPart 10 Specifications10.1 General CharacteristicsThe