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SHI Programming Considerations
DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2
Freescale Semiconductor 7-21
7.7.2 SPI Master Mode
The SPI Master mode is initiated by enabling the SHI (HEN = 1), selecting the SPI mode (HI
2
C = 0), and
selecting the Master mode of operation (HMST = 1). Before enabling the SHI as an SPI master device, the
programmer should program the proper clock rate, phase, and polarity in HCKR. When configured in the
SPI Master mode, the SHI external pins operate as follows:
• SCK/SCL is the SCK serial clock output.
• MISO/SDA is the MISO serial data input.
• MOSI/HA0 is the MOSI serial data output.
•SS/HA2 is the SS input. It should be kept deasserted (high) for proper operation.
•HREQ is the Host Request input.
The external slave device can be selected either by using external logic or by activating a GPIO pin
connected to its SS pin. However, the SS input pin of the SPI master device should be held deasserted
(high) for proper operation. If the SPI master device SS pin is asserted, the Host Bus Error status bit
(HBER) is set. If the HBIE bit is also set, the SHI issues a request to the DSP interrupt controller to service
the SHI Bus Error interrupt.
In the SPI Master mode the DSP must write to HTX to receive, transmit, or perform a full-duplex data
transfer. Actually, the interface performs simultaneous data receive and transmit. The status bits of both
receive and transmit paths are active; however, the programmer may disable undesired interrupts and
ignore non-relevant status bits. In a data transfer, the HTX is transferred to IOSR, clock pulses are
generated, the IOSR data is shifted out (via MOSI) and received data is shifted in (via MISO). The DSP
programmer may write HTX (if the HTDE status bit is set) using either DSP instructions or DMA transfers
to initiate the transfer of the next word. The HRX FIFO contains valid receive data, which may be read by
the DSP using either DSP instructions or DMA transfers, if the HRNE status bit is set.
NOTE
Freescale recommends that an SHI individual reset (HEN cleared) be
generated before beginning data reception in order to reset the receive FIFO to
its initial (empty) state, such as when switching from transmit to receive data.
The HREQ input pin is ignored by the SPI master device if the HRQE[1:0] bits are cleared, and considered
if any of them is set. When asserted by the slave device, HREQ indicates that the external slave device is
ready for the next data transfer. As a result, the SPI master sends clock pulses for the full data word transfer.
HREQ is deasserted by the external slave device at the first clock pulse of the new data transfer. When
deasserted, HREQ will prevent the clock generation of the next data word transfer until it is asserted again.
Connecting the HREQ
line between two SHI-equipped DSPs, one operating as an SPI master device and
the other as an SPI slave device, enables full hardware handshaking if CPHA = 1. For CPHA = 0, HREQ
should be disabled by clearing HRQE[1:0].
7.7.3 I
2
C Slave Mode
The I
2
C Slave mode is entered by enabling the SHI (HEN = 1), selecting the I
2
C mode (HI
2
C = 1), and
selecting the Slave mode of operation (HMST = 0). In this operational mode the contents of HCKR are
ignored. When configured in the I
2
C Slave mode, the SHI external pins operate as follows:
- Processor 1
- Contents 3
- 3 Memory Configuration 4
- 4 Core Configuration 4
- Freescale Semiconductor v 5
- Freescale Semiconductor vii 7
- BookTitle, Rev. # 10
- List of Figures 11
- List of Tables 13
- Freescale Semiconductor xv 15
- Manual Conventions 16
- Freescale Semiconductor xvii 17
- 1 Overview 19
- 1.2 Features 20
- Audio Processor Architecture 21
- Freescale Semiconductor 1-3 21
- 1.5.1 Data ALU 22
- 1.5.1.1 Data ALU Registers 23
- 1.5.4 Internal Buses 24
- Freescale Semiconductor 1-7 25
- 1.6.3 Bootstrap ROM 26
- 1.6.1 Reserved Memory Spaces 26
- 1.6.5 External Memory Support 27
- 1.8 Status Register (SR) 28
- 2.1 Signal Groupings 29
- DSP56364 30
- 2.2 Power 31
- 2.3 Ground 31
- 2.5.1 External Address Bus 32
- 2.5.2 External Data Bus 33
- 2.5.3 External Bus Control 33
- After RESET 34
- 2.7 Serial Host Interface 35
- 2.9 JTAG/OnCE Interface 41
- 2.10 GPIO Signals 42
- 3.1.1 Program Memory Space 43
- 3.1.2 Data Memory Spaces 44
- 3.1.2.2 X Data RAM 45
- 3.1.2.3 Y Data Memory Space 45
- 3.1.2.4 Y Data RAM 45
- 3.3.1 RAM Locations 46
- 3.3.2 ROM Locations 46
- Internal Memory Configuration 47
- Freescale Semiconductor 3-5 47
- 3.4 Memory Maps 48
- Memory Maps 49
- Freescale Semiconductor 3-7 49
- 3.5 External Memory Support 50
- 3.6 Internal I/O Memory Map 50
- 4.2.1 Mode C (MC) - Bit 2 52
- 4.3 Operating Modes 53
- 4.4 Bootstrap Program 54
- Interrupt Priority Registers 56
- 4-6 Freescale Semiconductor 56
- 4.6 DMA Request Sources 57
- 4.7 PLL and Clock Generator 57
- 5.1 Introduction 61
- 5.2 GPIO Programming Model 61
- GPIO Programming Model 64
- 5-4 Freescale Semiconductor 64
- 6.1 Introduction 65
- Introduction 66
- 6-2 Freescale Semiconductor 66
- ESAI Data and Control Pins 67
- Freescale Semiconductor 6-3 67
- 6-4 Freescale Semiconductor 68
- 6.3 ESAI Programming Model 71
- Figure 6-2 TCCR Register 72
- Freescale Semiconductor 6-9 73
- 6-10 Freescale Semiconductor 74
- 6-12 Freescale Semiconductor 76
- Figure 6-5 TCR Register 77
- 6-14 Freescale Semiconductor 78
- Freescale Semiconductor 6-15 79
- Normal Mode 81
- Network Mode 81
- Figure 6-14 82
- 6-20 Freescale Semiconductor 84
- Freescale Semiconductor 6-21 85
- 6-22 Freescale Semiconductor 86
- Figure 6-8 RCCR Register 87
- Figure 6-9 RCR Register 91
- 6-28 Freescale Semiconductor 92
- Freescale Semiconductor 6-31 95
- Figure 6-10 SAICR Register 96
- Freescale Semiconductor 6-33 97
- 6-34 Freescale Semiconductor 98
- Figure 6-12 SAISR Register 99
- ESAI Programming Model 100
- 6-36 Freescale Semiconductor 100
- Freescale Semiconductor 6-37 101
- 6-38 Freescale Semiconductor 102
- (a) Receive Registers 103
- (b) Transmit Registers 103
- Freescale Semiconductor 6-41 105
- Figure 6-15 TSMA Register 106
- Figure 6-16 TSMB Register 106
- Figure 6-17 RSMA Register 107
- Figure 6-18 RSMB Register 107
- 6.4.1 ESAI After Reset 108
- 6.4.2 ESAI Initialization 108
- 6.4.3 ESAI Interrupt Requests 109
- Operating Modes 110
- 6-46 Freescale Semiconductor 110
- 6.4.4.3 Frame Sync Selection 111
- 6.4.5 Serial I/O Flags 112
- Figure 6-19 PCRC Register 113
- Figure 6-20 PRRC Register 113
- Figure 6-21 PDRC Register 114
- ESAI Initialization Examples 115
- Freescale Semiconductor 6-51 115
- 6-52 Freescale Semiconductor 116
- 7 Serial Host Interface 117
- 7-2 Freescale Semiconductor 118
- 7.3 SHI Clock Generator 119
- 7-4 Freescale Semiconductor 120
- 7-6 Freescale Semiconductor 122
- 7.4.4.2 HSAR I 123
- 7-8 Freescale Semiconductor 124
- Freescale Semiconductor 7-9 125
- Table 7-4 SHI Data Size 127
- Freescale Semiconductor 7-15 131
- 7.5 SPI Bus Characteristics 132
- 7.6.1 Overview 133
- C Bus Characteristics 134
- 7-18 Freescale Semiconductor 134
- C Data Transfer Formats 135
- 7.7.1 SPI Slave Mode 136
- 7.7.2 SPI Master Mode 137
- C Slave Mode 137
- 7.7.3.1 Receive Data in I 138
- C Master Mode 139
- 7.7.4.1 Receive Data in I 140
- 7.7.4.2 Transmit Data In I 141
- 7-26 Freescale Semiconductor 142
- Appendix A Bootstrap ROM 143
- A-2 Freescale Semiconductor 144
- Freescale Semiconductor A-3 145
- A-4 Freescale Semiconductor 146
- Freescale Semiconductor A-5 147
- A-6 Freescale Semiconductor 148
- Freescale Semiconductor A-7 149
- A-8 Freescale Semiconductor 150
- Appendix B BDSL File 151
- B-2 Freescale Semiconductor 152
- Freescale Semiconductor B-3 153
- B-4 Freescale Semiconductor 154
- Freescale Semiconductor B-5 155
- B-6 Freescale Semiconductor 156
- C.1.1 Peripheral Addresses 157
- C.1.2 Interrupt Addresses 157
- C.1.3 Interrupt Priorities 157
- Programmer’s Reference 158
- C.2 Programming Sheets 164
- Central Processor 165
- =Reserved, program as 1 166
- CENTRAL PROCESSOR 167
- C-12 Freescale Semiconductor 168
- Bits XTLR and 169
- C-14 Freescale Semiconductor 170
- SHI Host Receive 171
- C-16 Freescale Semiconductor 172
- X: $FFFFB6 Reset: $000000 173
- X: $FFFFB5 Reset: $000000 174
- X: $FFFFB8 Reset: $000000 175
- X: $FFFFB7 Reset: $000000 176
- X: $FFFFB4 Reset: $000000 177
- SAISR - ESAI Status Register 178
- X: $FFFFB3 Reset $000000 178
- Freescale Semiconductor C-23 179
- C-24 Freescale Semiconductor 180
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