Freescale-semiconductor ColdFire MCF52210 Manual de usuario descargar pdf (Pagina 191)

100

101

System Control Module (SCM)

MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2

Freescale Semiconductor 12-15

IPSBAR

Offset:

0x0024 + Offset (PACRn) Access: read/write

76543210

LOCK1 ACCESS_CTRL1 LOCK0 ACCESS_CTRL0

Reset:00000000

Figure 12-9. Peripheral Access Control Register (PACRn)

Table 12-10. PACR Field Descriptions

Field Description

LOCK1

This bit, when set, prevents subsequent writes to ACCESSCTRL1. Any attempted write to the PACR

generates an error termination and the contents of the register are not affected. Only a system reset clears

this flag.

6–4

ACCESS_CTRL1

This 3-bit field defines the access control for the given platform peripheral.

The encodings for this field are shown in Table 12-11.

LOCK0

This bit, when set, prevents subsequent writes to ACCESSCTRL0. Any attempted write to the PACR

generates an error termination and the contents of the register are not affected. Only a system reset clears

this flag.

2–0

ACCESS_CTRL0

This 3-bit field defines the access control for the given platform peripheral.

The encodings for this field are shown in Table 12-11.

Table 12-11. PACR ACCESSCTRL Bit Encodings

Bits Supervisor Mode User Mode

000 Read/Write No Access

001 Read No Access

010 Read Read

011 Read No Access

100 Read/Write Read/Write

101 Read/Write Read

110 Read/Write Read/Write

111 No Access No Access

Table 12-12. Peripheral Access Control Registers (PACRs)

IPSBAR Offset Name

Modules Controlled

ACCESS_CTRL1 ACCESS_CTRL0

0x024 PACR0 SCM —

0x025 PACR1 — DMA

0x026 PACR2 UART0 UART1

1 2 ... 186 187 188 189 190 191 192 193 194 195 196 ... 575 576

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