Freescale-semiconductor ColdFire MCF52210 Manual de usuario descargar pdf (Pagina 130)

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Power Management

MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2

8-2 Freescale Semiconductor

8.2.1 Peripheral Power Management Registers (PPMRH, PPMRL)

The PPMRH and PPMRL registers provide a bit map for controlling the generation of the module clocks

for each decoded address space associated with the IPS controller. The PPMRx provides a unique control

bit for each of these address spaces that defines whether the module clock for the given space is enabled

or disabled.

NOTE

It is software’s responsibility to appropriately disable module clocks using

the PPMRx only when a module is completely unused or quiescent.

Because the operation of the IPS controller and the system control module (SCM) are fundamental to the

operation of the system, the clocks for these three modules cannot be disabled.

The individual bits of the PPMRx can be modified using a read-modify-write to this register directly or

indirectly through writes to the PPMRS and PPMRC registers to set/clear individual bits.

See Figure 8-1 and Table 8-2 for the PPMRH definition.

IPSBAR

Offset: 0x000C (PPMRH)

Access: read/write

31 30 29 28 27 26 25 24

R 0 0 0 0 0 000

Reset 0 0 0 0 0 0 0 0

23 22 21 20 19 18 17 16

R0 0 0 0 0 000

Reset 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8

R 0 000

CDCFM

CDPWM CDGPT

Reset 0 0 0 0 0 0 0 0

76 5 43210

CDADC

CDPIT1 CDPIT0

CDEPORT CDPORTS

Reset 0 0 0 0 0 0 0 0

Figure 8-1. Peripheral Power Management Register High (PPMRH)

1 2 ... 125 126 127 128 129 130 131 132 133 134 135 ... 575 576

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