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Timer Modes of Operation

DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4

11-20 Freescale Semiconductor

11.4.4.2 Watchdog Toggle (Mode 10)

In this mode, the timer generates an interrupt at a preset rate. Timer 0 also toggles the output on TIO0.

Set the TE bit to clear the counter and enable the timer. The value the timer is to count is loaded into the

TPCR. The counter is loaded with the TLR value on the first timer clock received from either the

DSP56366 internal clock divided by two (CLK/2) or the prescaler clock output. Each subsequent timer

clock increments the counter. The TIO0 signal is set to the value of the INV bit.

When the counter equals the value in the TCPR, the TCF bit in the TCSR is set, and a compare interrupt

is generated if the TCIE bit is also set. If the TRM bit is set, the counter is loaded with the TLR value on

the next timer clock and the count is resumed. If the TRM bit is cleared, the counter continues to be

incremented on each subsequent timer clock

When counter overflow has occurred, the polarity of the TIO0 output pin is inverted, the TOF bit in the

TCSR is set, and an overflow interrupt is generated if the TOIE bit is also set. The TIO0 polarity is

determined by the INV bit.

The counter is reloaded whenever the TLR is written with a new value while the TE bit is set. This process

is repeated until the timer is disabled by clearing the TE bit. The counter contents can be read at any time

by reading the TCR register.

NOTE

In this mode, internal logic preserves the TIO0 value and direction for an

additional 2.5 internal clock cycles after the DSP56366 hardware RESET

signal is asserted. This ensures that a valid RESET signal is generated when

the TIO0 signal is used to reset the DSP56366.

11.4.5 Reserved Modes

Modes 8, 11, 12, 13, 14, and 15 are reserved.

11.4.6 Special Cases

The following special cases apply during wait and stop state.

11.4.6.1 Timer Behavior during Wait

Timer clocks are active during the execution of the WAIT instruction and timer activity is undisturbed. If

a timer interrupt is generated, the DSP56366 leaves the wait state and services the interrupt.

Bit Settings Mode Characteristics

TC3 TC2 TC1 TC0 Mode NAME Kind TIO0 Clock

1010 10 Toggle WatchdogOutputInternal

1 2 ... 245 246 247 248 249 250 251 252 253 254 255 ... 365 366

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Freescale Semiconductor DSP56366 Manual de usuario Pagina 250